Resistive memory architectures with multiple memory cells per access device

ABSTRACT

A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

CROSS REFERENCES

The present application for patent is a continuation application of U.S.patent application Ser. No. 17/018,554 by Liu et al., entitled“Resistive Memory Architectures With Multiple Memory Cells Per AccessDevice,” filed Sep. 11, 2020, which is a divisional application of U.S.patent application Ser. No. 16/542,174 by Liu et al., entitled“Resistive Memory Architectures With Multiple Memory Cells Per AccessDevice,” filed Aug. 15, 2019, which is a continuation application ofU.S. patent application Ser. No. 15/976,462 by Liu et al., entitled“Resistive Memory Architectures With Multiple Memory Cells Per AccessDevice,” filed May 10, 2018, which is a continuation application of Ser.No. 15/266,859 by Liu et al., entitled “Resistive Memory ArchitecturesWith Multiple Memory Cells Per Access Device,” filed Sep. 15, 2016,which is a continuation application of U.S. patent application Ser. No.14/617,377 by Liu et al., entitled “Resistive Memory Architectures WithMultiple Memory Cells Per Access Device,” filed Feb. 9, 2015, which is adivisional application of U.S. patent application Ser. No. 13/292,884 byLiu et al., entitled “Resistive Memory Architectures With MultipleMemory Cells Per Access Device,” filed Nov. 9, 2011, which is acontinuation application of U.S. patent application Ser. No. 12/656,720by Liu et al., entitled “Resistive Memory Architectures With MultipleMemory Cells Per Access Device,” filed Feb. 16, 2010, which is adivisional application of U.S. patent application Ser. No. 11/806,495 byLiu et al., entitled “Resistive Memory Architectures With MultipleMemory Cells Per Access Device,” filed May 31, 2007, each of which isassigned to the assignee hereof, and each of which is expresslyincorporated by reference in its entirety herein.

FIELD OF THE INVENTION

The embodiments of the invention relate generally to the field ofsemiconductor devices and, more particularly, to resistive memorydevices, e.g., phase change memory devices.

BACKGROUND OF THE INVENTION

Microprocessor-accessible memory devices have traditionally beenclassified as either non-volatile or volatile memory devices.Non-volatile memory devices are capable of retaining stored informationeven when power to the memory device is turned off. Traditionally,however, non-volatile memory devices occupy a large amount of space andconsume large quantities of power, making these devices unsuitable foruse in portable devices or as substitutes for frequently-accessedvolatile memory devices. On the other hand, volatile memory devices tendto provide greater storage capability and programming options thannon-volatile memory devices. Volatile memory devices also generallyconsume less power than non-volatile devices. However, volatile memorydevices require a continuous power supply in order to retain storedmemory content.

Research and development of commercially viable memory devices that arerandomly accessed, have relatively low power consumption, and arenon-volatile is ongoing. One ongoing area of research is in resistivememory cells where resistance states can be programmably changed. Oneavenue of research relates to devices that store data in memory cells bystructurally or chemically changing a physical property of the memorycells in response to applied programming voltages, which in turn changecell resistance. Examples of variable resistance memory devices beinginvestigated include memories using variable resistance polymers,perovskite, doped amorphous silicon, phase-changing glasses, and dopedchalcogenide glass, among others.

FIG. 1 shows a basic composition of a typical variable resistance memorycell such as a phase change memory cell 10 constructed over a substrate12, having a variable resistance material, e.g., a phase change material16 formed between a bottom electrode 14 and a top electrode 18. One typeof variable resistance material may be amorphous silicon doped with V,Co, Ni, Pd, Fe and Mn as disclosed in U.S. Pat. No. 5,541,869 to Rose etal. Another type of variable resistance material may include perovskitematerials such as Pr_((1_x))Ca_(x)MnO₃ (PCMO), La_((1-x))Ca_(x)MnO₃(LCMO), LaSrMnO₃ (LSMO), GdBaCo_(x)O_(y) (GBCO) as disclosed in U.S.Pat. No. 6,473,332 to Ignatiev et al. Still another type of variableresistance material may be a doped chalcogenide glass of the formulaA_(x)B_(y), where “B” is selected from among S, Se and Te and mixturesthereof, and where “A” includes at least one element from Group III-A(B, Al, Ga, In, TI), Group IV-A (C, Si, Ge, Sn, Pb), Group V-A (N, P,As, Sb, Bi), or Group VII-A (F, Cl, Br, I, At) of the periodic table,and with the dopant being selected from among the noble metals andtransition metals, including Ag, Au, Pt, Cu, Cd, Ir, Ru, Co, Cr, Mn orNi, as disclosed in U.S. Pat. Nos. 6,881,623 and 6,888,155 to Campbellet al. and Campbell, respectively. Yet another type of variableresistance material includes a carbon-polymer film comprising carbonblack particulates or graphite, for example, mixed into a plasticpolymer, such as that disclosed in U.S. Pat. No. 6,072,716 to Jacobsonet al. The material used to form the electrodes 14, 18 can be selectedfrom a variety of conductive materials, such as tungsten, nickel,tantalum, titanium, titanium nitride, aluminum, platinum, or silver,among others.

Much research has focused on memory devices using memory elementscomposed of chalcogenides. Chalcogenides are alloys of Group VI elementsof the periodic table, such as Te or Se. A specific chalcogenidecurrently used in rewriteable compact discs (“CD-RWs”) is Ge₂Sb₂Te₅. Inaddition to having valuable optical properties that are utilized inCD-RW discs, Ge₂Sb₂Te₅ also has desirable physical properties as avariable resistance material. Various combinations of Ge, Sb and Te maybe used as variable resistance materials and which are hereincollectively referred to as GST materials. Specifically, GSTs can changestructural phases between an amorphous phase and two crystalline phases.The resistance of the amorphous phase (“a-GST”) and the resistances ofthe cubic and hexagonal crystalline phases (“c-GST” and “h-GST,”respectively) can differ significantly. The resistance of amorphous GSTis greater than the resistances of either cubic GST or hexagonal GST,whose resistances are similar to each other. Thus, in comparing theresistances of the various phases of GST, GST may be considered atwo-state material (amorphous GST and crystalline GST), with each statehaving a different resistance that can be equated with a correspondingbinary state. A variable resistance material such as GST whoseresistance changes according to its material phase is referred to as aphase change material.

The transition from one GST phase to another occurs in response totemperature changes of the GST material. The temperature changes, i.e.,the heating and cooling, can be caused by passing differing amounts ofcurrent through the GST material. The GST material is placed in acrystalline state by passing a crystallizing current through the GSTmaterial, thus warming the GST material to a temperature wherein acrystalline structure may grow. A stronger melting current is used tomelt the GST material for subsequent cooling to an amorphous state. Asthe typical phase change memory cell uses the crystalline state torepresent one logical state binary, e.g., “1,” and the amorphous stateto represent another logical state binary, e.g., “0,” the crystallizingcurrent is referred to as a set current 'SET and the melting current isreferred to as an erase or reset current I_(RST). One skilled in the artwill understand, however, that the assignment of GST states to binaryvalues may be switched if desired. The set currents I_(SET) and theerase or reset currents I_(RST) are typically large, often in the orderof a few hundred microamps.

A typical resistive memory bit structure such as a phase change memorybit structure 315 that incorporates a phase change memory cell 10, forexample, is represented schematically in FIG. 2A. In FIG. 2A, the memorycell 10 is connected to a cell select line 320 via either the cell's topor bottom electrode. The opposing electrode is connected to an accessdevice 350 such as an access transistor. The access device 350 is gatedby a word line 330. A bit line 340 provides a source to the accessdevice 350 and is connected to the memory cell 10 when the access device350 is activated by the word line 330. The access device 350 must besufficiently large in order to pass the large phase changing currentsI_(SET) and I_(RST) to the memory cell 10.

The memory bit structure 315 of FIG. 2A may be arranged into an array ofmemory bit structures, as illustrated in FIG. 2B. In FIG. 2B, aconventional resistive memory device 400 includes an array of memory bitstructures 315 a-315 h. The memory bit structures 315 a-315 h arearranged in rows and columns. The rows and columns may be partiallystaggered, as in FIG. 2B, or may be aligned in parallel. The memory bitstructures 315 a-315 h along any given cell select line 320 a-320 d donot share a common word line 330 a-330 d. Additionally, the memory bitstructures 315 a-315 h along any given word line 330 a-330 d do notshare a common bit line 340 a-340 d. In this manner, each memory bitstructure is uniquely identified by the combined selection of the wordline to which the gate of the memory cell access device 350 a-350 h isconnected, and the cell select line to which the memory cell isconnected.

Each word line 330 a-330 d is connected to a word line driver in theform of a row decoder 460 for selecting the respective word line for anaccess operation. Similarly, each cell select line 320 a-320 d iscoupled to a driver in the form of a column decoder 450.

For simplicity, FIG. 2B illustrates a memory array having only four rowsof memory bit structures 315 on four cell select lines 320 a-320 d andfour columns of memory bit structures 315 on four word lines 330 a-330d. However, it should be understood that in practical applications, thememory device 400 has significantly more memory bit structures in anarray. For example, an actual memory device may include several millionmemory bit structures 315 arranged in a number of subarrays.

Significantly, FIGS. 2A and 2B illustrate how each memory cell 10 isconnected to a separate and individual access device 350. As wasdescribed above, in resistive memory cells such as the phase changememory cells 10, the amount of current necessary to change at least aportion of the phase change material 16 into an amorphous state isrelatively high (generally a few hundred microamps). As a result, theaccess device 350 for each memory cell 10 is correspondingly large. In aconventional phase change memory bit structure with a one-to-onecorrespondence between memory cells and access devices, the typicalmemory bit area is 16 F², meaning an area equal to 16 F², where F is thefabrication resolution. Because of continued desire to reduce theoverall footprint of memory bit structures, there is a need to reducethe footprint of resistive memory bit structures, e.g., phase changememory bit structures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a typical phase change memory cell.

FIGS. 2A, 2B and 2C are schematic and physical representations of aphase change memory bit structure and a corresponding memory device.

FIG. 3 is a schematic representation of a phase change memory bitstructure according to a disclosed embodiment.

FIGS. 4A, 4B, 4C and 4D are schematic and physical representations of aphase change memory bit structure and a corresponding memory deviceaccording to a disclosed embodiment.

FIGS. 5A, 5B, 5C and 5D are representative diagrams and flowcharts ofthe formation of a rectifying device in a phase change memory bitstructure according to a disclosed embodiment.

FIGS. 6A, 6B and 6C are schematic and physical representations of aphase change memory bit structure and a corresponding memory deviceaccording to a disclosed embodiment.

FIGS. 7A, 7B and 7C are schematic and physical representations of aphase change memory bit structure and a corresponding memory deviceaccording to a disclosed embodiment.

FIGS. 8A, 8B, 8C and 8D are schematic and physical representations of aphase change memory bit structure and a corresponding memory deviceaccording to a disclosed embodiment.

FIGS. 9A, 9B and 9C are schematic and physical representations of aphase change memory bit structure and a corresponding memory deviceaccording to a disclosed embodiment.

FIGS. 10A, 10B and 10C are schematic and physical representations of aphase change memory bit structure and a corresponding memory deviceaccording to a disclosed embodiment.

FIGS. 11A, 11B, 11C and 11D are schematic and physical representationsof a phase change memory bit structure and a corresponding memory deviceaccording to a disclosed embodiment.

FIG. 12 illustrates a processor system that includes a memory deviceaccording to a disclosed embodiment.

FIGS. 13A, 13B and 13C are schematic and physical representations of aphase change memory bit structure and a corresponding memory deviceaccording to a disclosed embodiment.

FIGS. 14A, 14B and 14C are schematic and physical representations of aphase change memory bit structure and a corresponding memory deviceaccording to a disclosed embodiment.

FIGS. 15A, 15B and 15C are schematic and physical representations of aphase change memory bit structure and a corresponding memory deviceaccording to a disclosed embodiment.

DETAILED DESCRIPTION OF THE INVENTION

The large current requirements in variable resistance memory cellsresult in large access devices. When a variable resistance memory bitstructure has a one-to-one pairing of memory cells to access devices,the memory bit structure has a large footprint. An example of thephysical structure of a one-to-one memory cell to access device pairingis shown in FIG. 2C, which relates to portions of memory device 400(FIG. 2B). In FIG. 2C, a cross-sectional view of the physicalorganization of two conventional memory bit structures 315 c, 315 e isdepicted. The memory bit structures 315 c, 315 e share the same cellselect line 320 b and bit line 340 b. Each memory bit structure 315 c,315 e in FIG. 2C includes a memory cell 10 a, 10 b, respectively, thateach include a top electrode 18, a bottom electrode 14, and a phasechange region 16 positioned in between the electrodes 14, 18. The topelectrode 18 of both memory cells 10 a, 10 b is connected to the cellselect line 320 b. The bottom electrode 14 of each memory cell 10 a, 10b is connected to the drains of separate and individual access devices350 c, 350 e. The opposing sources of the access devices 350 c, 350 eare connected to a shared bit line 340 b. The access devices 350 c, 350e are gated by separate word lines 330 b, 330 c, which form gates ofaccess devices 350 c, 350 e.

Generally, the two access devices 350 c, 350 e are located in a singleactive area 552 of the memory device 400. Other pairs of access devicesare located in neighboring active areas 552. Active areas 552 areregions of device 400 that have been doped so as to allow formation ofone or more access devices 350, such as transistors. Because the currentdemands of resistive memory cells 10 are relatively high, the size ofthe access devices 350, and hence the size of the active areas 552 arecorrespondingly large.

The large access devices and active areas have the potential to resultin large memory bit structure footprints and sparsely populated memorydevices, as illustrated in FIG. 2B. An improved resistive memory bitstructure with a reduction in the memory bit structure footprint wouldallow the fabrication of denser resistive memory devices.

Embodiments of the invention are now disclosed which provide differentways of reducing the resistive memory bit structure footprint. Onemethod of reducing the area required by a phase change memory bitstructure and yet still utilizing an access device large enough for thephase-changing currents used in a phase change memory cell is to usemore than one memory cell per access device. For example, FIG. 3illustrates a phase change memory bit structure 615 that incorporatestwo phase change memory cells 10 a, 10 b. Memory cells 10 a, 10 b areboth coupled to an access device 350 such as a transistor. Each memorycell 10 a, 10 b is also connected to a separate cell select line 320 a,320 b. As in the typical phase change memory bit structure 315 of FIG.2A, the access device 350 is gated by a word line 330. A bit line 340provides a source to the access device 350 and is connected to thememory cells 10 a, 10 b when the access device 350 is activated by theword line 330 and when one of the memory cells 10 a, 10 b is selected bythe corresponding cell select line 320 a, 320 b, respectively.

The memory bit structure 615 also includes two rectifying devices 660 a,660 b such as, for example, diodes. The rectifying devices 660 a, 660 bare each serially connected between the corresponding memory cells 10 a,10 b and the access device 350. The rectifying devices 660 a, 660 bprevent parallel leakage current among the memory cells 10 a, 10 b. Inother words, when memory cell 10 a is selected by activation of both thecell select line 320 a and word line 330, the resultant current thatflows through memory cell 10 a is prevented from flowing through memorycell 10 b by rectifying device 660 b. As will be explained below, therectifying devices 660 a, 660 b may be integrated into the drain regionsof the access device 350 when access device 350 is a transistor, or maybe separate devices.

Multiple memory bit structures 615 may be organized into an array. FIG.4A illustrates a memory device 700 in which memory bit structures 615a-6151 are organized as parallel structures (as opposed to the staggeredarrangement illustrated in FIG. 2B). As in the memory device depicted inFIG. 2B, device 700 includes word lines 330 a-330 d, each connected to aword line driver in the form of a row decoder 460 for selecting therespective word line for an access operation. Similarly, device 700includes cell select lines 320 a-320 f which are each coupled to adriver in the form of a column decoder 450. For each memory bitstructure, two cell select lines and one word line are required, sinceeach memory bit structure includes two memory cells. For example, inFIG. 4A, memory bit structure 615 d is connected to both cell selectlines 320 a and 320 b as well as to the word line 330 b. In order toselect memory cell 10 c, for example, cell select line 320 a and wordline 330 b must both be activated. The current passing through theselected memory cell 10 c may then be measured by sense amplifiers (notshown), in the case of a read operation. In the case of a writeoperation, a stronger programming current is applied to the memory cell.A write operation for memory cell 10 c is done by selecting memory cell10 c through activation of both the cell select line 320 a and the wordline 330 b. A voltage differential between the cell select line 320 aand the bit line 340 a sufficient to generate a current to program thememory cell 10 c is created. The voltage differential may be created byaltering the voltages of either the cell select line 320 a or the bitline 340 a, or through some combination. Generally, the bit lines 340a-340 c are either tied to ground or to a fixed voltage, though they maybe individually addressed.

A cross-sectional view of the physical organization of two memory bitstructures 615 a, 615 d (FIG. 4A) in device 700 is represented in FIGS.4B and 4C. FIGS. 4B and 4C represent two different cross sectional viewsover a single active area 852, as illustrated in the top-down view ofFIG. 4D. The cross-sectional views appear similar, however each viewincludes a different cell select line 320 a (FIG. 4B), 320 b (FIG. 4C),different memory cells 10 a, 10 c (FIG. 4B), 10 b, 10 d (FIG. 4C), anddifferent rectifying devices 660 a, 660 c (FIG. 4B), 660 b, 660 d (FIG.4C). A single memory bit structure 615 a, 615 d (FIG. 4A) includeselements of both FIGS. 4B and 4C. Memory bit structure 615 a (FIG. 4A)includes word line 330 a for activating access device 350 a. When accessdevice 350 a is activated, bit line 340 a is coupled to both memorycells 10 a (FIG. 4B) and 10 b (FIG. 4C) via lower metal layer 1. The topelectrode of memory cell 10 a is connected to cell select line 320 a(FIG. 4B). The top electrode of memory cell 10 b, however, is coupled tocell select line 320 b (FIG. 4C). Thus, memory cells 10 a and 10 b sharethe same word line 330 a, bit line 340 a and access device 350 a, butare coupled to different cell select lines 320 a, 320 b. Similarly,memory bit structure 615 d (FIG. 4A) includes word line 330 b foractivating access device 350 d. When access device 350 d is activated,bit line 340 a is coupled to both memory cells 10 c (FIG. 4B) and 10 d(FIG. 4C) via lower metal layer 1. Memory cell 10 d is coupled to cellselect line 320 b (FIG. 4C) and memory cell 10 c is coupled to cellselect line 320 a (FIG. 4B).

Each memory cell 10 a-10 d is coupled to an access device 350 a, 350 dvia a respective rectifying device 660 a-660 d. The rectifying devices660 a-660 d may be p-n or Schottky diodes formed in the drains of theaccess devices 350. Multiple rectifying devices are located within asingle access device drain. For example, both memory cells 10 a, 10 bare coupled to rectifying devices 660 a, 660 b located within the drainof access device 350 a. The rectifying devices 660 a, 660 b may includedoped regions that are physically separate from each other, as indicatedin FIG. 4D, or they may share a doped region. In either case, however,the rectifying devices 660 a, 660 b function as two separate devices.Similarly, rectifying devices 660 c, 660 d are located within the drainof access device 350 d and may include doped regions that are physicallyseparate from each other or that are shared.

FIG. 4D is a top-view schematic diagram of active area 852. FIG. 4Dillustrates the physical relationship of the cross-sectional views ofFIGS. 4B and 4C to each other. Both cross-sectional views are takenabove the same active area 852. Each cross-sectional view is locatedover two doped regions that are part of the rectifying devices 660 a-660d, as explained below in connection with FIGS. 5A and 5B. The activearea 852 is host to two access devices 350 a, 350 d. Access device 350 ais illustrated as including the upper portion of active area 852 and isbisected by word line 330 a. Access device 350 d is illustrated asincluding the lower portion of active area 852 and is bisected by wordline 330 b. Both access devices 350 a, 350 d share bit line 340 a as asource.

As stated above, the rectifying devices 660 a-660 d may be formed withinthe drains of the access devices 350 a, 350 d. For example, FIG. 5Aillustrates a rectifying device 660 formed as a p-n diode in the drainof access device 350 gated by word line 330. Method 510 (FIG. 5B) isused to form the p-n diode illustrated in FIG. 5A. The components of theaccess device 350 are formed (step 503), such as the gate 584 and thesource (not shown in FIG. 5B). The access device drain 582 is alsoformed and then heavily doped with, for example, arsenic or phosphorous(step 503). After the access device 350 is formed, inter-leveldielectrics (ILD) 586 such as silicon dioxide are deposited inpreparation for metal trace deposition and excess deposits are removedvia chemical-mechanical polishing (CMP) (step 504). A via 588 is thenetched through the deposited dielectrics 586, extending to the accessdevice drain 582 (step 506). Boron implantation is used to dope thebottom of the via 588 to p-type (step 520). An annealing process is usedto cause the p-type doping to diffuse sideways so as to cover the entirebottom of the via 588 (step 520). The via 588 is then filled with a thindeposited layer of titanium 590 followed by a thin deposited layer oftitanium nitride 591 and then tungsten 592 (step 522). An annealingprocess is again used, this time to form titanium silicide (TiSi₂) 593from the initially deposited layer of titanium 590 at the bottom of thevia 588, thus reducing the contact resistance (step 524). Finally,tungsten chemical-mechanical polishing is used to form the tungstencontacts 594 (step 524).

The rectifying devices 660 may also be Schottky diodes, as illustratedin FIG. 5C and method 512 of FIG. 5D. A Schottky diode formation methodis similar to the p-n diode formation. In order to form a Schottky diodewithin the drain 582 of an access device 350, the portions of the accessdevice 350 are formed and the access device drain 582 heavily dopedwith, for example, arsenic or phosphorous (step 503). After the accessdevice 350 is formed, inter-level dielectrics (ILD) 586 such as silicondioxide are deposited in preparation for metal trace deposition andexcess deposits are removed via chemical-mechanical polishing (CMP)(step 504). A via 588 is then etched through the deposited dielectrics586, extending to the access device drain 582 (step 506). Boronimplantation is used to antidope the bottom of the via 588 to n-type(step 530). An annealing process is used to cause the n-type doping todiffuse sideways so as to cover the entire bottom of the via 588 (step530). The via 588 is then filled with deposited platinum 595 (step 532).An annealing process is again used, this time to form platinum silicide(PtSi) 596 at the bottom of the via 588 to form the Schottky diode (step532). Finally, a dry etch back process or chemical-mechanical polishingis used to form the platinum contacts 597 (step 508).

As explained above, memory device 700 is one method of implementingmemory bit structure 615 (FIG. 3) into a memory array. However, moreefficient designs that conserve memory bit area may be used. Forexample, FIG. 6A illustrates an additional method of organizing thememory bit structures 615 a-615 f into an array. In the memory device800, memory cells from different memory bit structures are arrangedback-to-back with cell select lines 320 a-320 d intersecting theback-to-back memory cells. Physically, the back-to-back memory cellsrepresent two stacked memory cells, with the top memory cell beingarranged upside down, as is illustrated in FIG. 6B, described below. Oneexample of back-to-back stacked memory cells are memory cells 10 a, 10e. As in the memory devices described above, device 800 includes wordlines 330 a-330 d and cell select lines 320 a-320 d. For each memory bitstructure 615 a-615 f, two cell select lines and one word line arerequired, since each memory bit structure 615 a-615 f includes twomemory cells. For example, in FIG. 6A, memory bit structure 615 a isconnected to both cell select lines 320 a and 320 b as well as the wordline 330 b. In order to select the memory cell 10 a, cell select line320 a and word line 330 b must both be activated. The current passingthrough the selected memory cell 10 a is then measured by senseamplifiers (not shown), in the case of a read operation. In the case ofa write operation, a stronger programming current is applied to thememory cell. A write operation for memory cell 10 a is done by selectingmemory cell 10 a through activation of both the cell select line 320 aand the word line 330 b. A voltage differential between the cell selectline 320 a and the bit line 340 b sufficient to generate a current toprogram the memory cell 10 a is created. The voltage differential may becreated by altering the voltages of either the cell select line 320 a orthe bit line 340 b, or through some combination. The bit lines 340 a-340d may be tied to ground or to a fixed voltage, or may be individuallyaddressed.

In FIG. 6B, a cross-sectional view of the physical organization of twomemory bit structures 615 a, 615 d (FIG. 6A) in device 800 isrepresented, in addition to partial depictions of other memory bitstructures. The portion of FIG. 6B represented by dashed lines is not inthe same cross-sectional plane as the portions of FIG. 6B represented bysolid lines, as also depicted in FIG. 6C. Memory bit structure 615 a(FIG. 6A) includes word line 330 b for activating access device 350 a.When access device 350 a is activated, bit line 340 b is coupled to bothmemory cells 10 a, 10 b via upper metal 2 and lower metal 1,respectively. Memory cell 10 a is an upside-down memory cell stacked ontop of a memory cell 10 e from another memory bit structure. The twomemory cells share the same top electrode 18 a, which is also shared bytwo additional stacked memory cells. Cell select line 320 a connectswith memory cell 10 a via the shared top electrode 18 a. Memory cell 10b is the lower of two stacked memory cells 10 f, 10 b and is coupled tocell select line 320 b via a top electrode 18 b. Similarly, memory bitstructure 615 d (FIG. 6A) includes word line 330 c for activating accessdevice 350 d. When access device 350 d is activated, bit line 340 b iscoupled to both memory cells 10 c, 10 d via lower metal 1 and uppermetal 2, respectively. Memory cell 10 d is an upside-down memory cellstacked on top of a memory cell 10 h from another memory bit structure,the two memory cells 10 d, 10 h sharing a top electrode 18 c. Cellselect line 320 a connects with memory cell 10 d via the shared topelectrode 18 c. Memory cell 10 c is the lower of two stacked memorycells 10 g, 10 c and is coupled to cell select line 320 b via its topelectrode 18 b.

In the arrangement of memory bit structures 615 in FIGS. 6A and 6B, eachmemory cell 10 a-10 d shares a top electrode 18 a-18 c and connectingcell select line 320 a, 320 b with three other memory cells. As aspecific example, memory cells 10 b, 10 c, 10 f, 10 g share topelectrode 18 b and are all connected to cell select line 320 b. However,each of the four memory cells are activated by a different word line(e.g., 330 a-330 d). Each access device 350 a, 350 d operates to allowcurrent flow through two different memory cells 10 a-10 d located abovedifferent active areas 852 a-852 c. For example, access device 350 acontrols access to memory cell 10 a located above active area 852 a andmemory cell 10 b located above active area 852 b. In this way, theoverall memory bit area is reduced through both a single accesstransistor servicing two memory cells as well as the stacking of memorycells on top of each other.

Each memory bit structure 615 a, 615 d also has rectifying devices 660a-660 d which, in this embodiment, have been formed within the drain ofthe access devices 350 a, 350 d. As in device 700 of FIGS. 4A-4D, therectifying devices 660 a-660 d may be formed using, for example, p-ndiodes or Schottky diodes, as explained in relation to FIGS. 5A and 5B.

FIG. 6C represents a top-down view of a portion of memory device 800. InFIG. 6C, each active area 852 a-852 c includes two access devices. Forexample, access devices 350 a and 350 d are in the active area 852 b.Within active area 852 b, access device 350 a is gated by word line 330b and, when activated, couples bit line 340 b to memory cells 10 a (FIG.6B), located above active area 852 a and memory cell 10 b (FIG. 6B),located above active area 852 b. Similarly, access device 350 d is gatedby word line 330 c and, when activated, couples bit line 340 b to memorycells 10 c, 10 d, located above active areas 852 b, 852 c, respectively.In each case, the controlling access device 350 a, 350 d controls accessto memory cells that are located above two adjacent but staggered activeareas (e.g., 852 a, 852 c). Memory cells that are located above activeareas that are adjacent to the active area wherein the controllingaccess device is located are coupled to their controlling access devicesvia a metal 2 trace and a rectifying device 660 a-660 d. The rectifyingdevice 660 a-660 d is formed within the drain of the controlling accessdevice 350 a, 350 d and is represented in FIG. 6C as a doped region 660a-660 d.

An additional method of organizing the memory bit structures 615 into anarray is illustrated in FIG. 7A. In FIG. 7A, memory device 900 includesmemory cells from different memory bit structures 615 a-615 d that arearranged back-to-back with cell select lines 320 a-320 c intersectingthe back-to-back memory cells. The primary difference between theorganization of memory device 800 and memory device 900 is that thememory bit structures 615 a-615 d in device 900 are arranged in aparallel manner and are not staggered as in device 800. The parallelstructure results in a tighter access device 350 a-350 d layout. Inorder to achieve the parallel layout, the two memory cells in eachmemory bit structure are arranged above diagonally proximate activeareas 852 a-852 d, as illustrated in FIG. 7C.

FIG. 7B represents a cross-sectional view of the physical organizationof two memory bit structures 615 a, 615 c in device 900. The portion ofFIG. 7B represented by dashed lines is not in the same cross-sectionalplane as the portions of FIG. 7B represented by solid lines. Memory bitstructure 615 a (FIG. 7A) includes word line 330 c for activating accessdevice 350 a. When access device 350 a is activated, bit line 340 b iscoupled to both memory cells 10 a, 10 b via upper metal 2 and lowermetal 1, respectively. Memory cell 10 a is an upside-down memory cellstacked on top of a memory cell 10 e from another memory bit structure.The two memory cells 10 a, 10 e share the same top electrode 18 a, whichis also shared by two additional stacked memory cells 10 c, 10 g. Cellselect line 320 a connects with memory cell 10 a via the shared topelectrode 18 a Memory cell 10 b is the lower of two stacked memory cells10 f, 10 b and is coupled to cell select line 320 b via a top electrode18 b. Similarly, memory bit structure 615 c (FIG. 7A) includes word line330 d for activating access device 350 c. When access device 350 c isactivated, bit line 340 b is coupled to both memory cells 10 c, 10 d vialower metal 1 and upper metal 2, respectively. Memory cell 10 c is anupside-down memory cell stacked on top of a memory cell 10 g fromanother memory bit structure, the two memory cells 10 c, 10 g sharing atop electrode 18 a. Cell select line 320 a connects with memory cell 10d via the shared top electrode 18 a. Memory cell 10 d is the lower oftwo stacked memory cells 10 h, 10 d and is coupled to cell select line320 b via its top electrode 18 b Bit lines 340 a-340 c are individuallyaddressed.

The arrangement of the memory bit structures 615 a-615 d in device 900differs from the physical arrangement of the memory bit structures indevice 800 in that the two memory bit structures 615 a, 615 c depictedin FIG. 7B are located above only two active areas, 852 a, 852 d. Indevice 800, three active areas are used to implement any pair of memorybit structures. The reduced number of active areas used by the memorybit structures 615 a-615 d in device 900 allows the active areas 852a-852 d to be arranged in a parallel orientation (as opposed to astaggered orientation as depicted in FIG. 6C).

In the top-down view of FIG. 7C, each active area 852 a-852 d includestwo access devices. The access devices 350 a and 350 c that controlaccess to the memory bit structures 615 a and 615 c are both located inactive area 852 d. Within active area 852 d, access device 350 a isgated by word line 330 c and, when activated, couples bit line 340 b tomemory cell 10 a (FIG. 7B) located above active area 852 a and memorycell 10 b (FIG. 7B) located above active area 852 d. Similarly, accessdevice 350 c is gated by word line 330 d and, when activated, couplesbit line 340 b to memory cells 10 c, 10 d, also located above activeareas 852 d and 852 a, respectively. In both cases, access devices 350a, 350 c control access to memory cells that are located in twodifferent active areas 852 a, 852 d.

FIGS. 13A-13C represent a similar circuit (memory device 2300 in FIG.13A), organization and arrangement as shown in FIGS. 7A-7C. However, inFIGS. 13A-13C, more than one memory cell shares the same cell selectline and word line. For example, in FIG. 13A, memory bit structures 615a and 615 b include memory cells 10 b, 10 c, respectively. Both memorycells 10 b, 10 c are activated by utilizing cell select line 320 b andword line 330 a. As a result, memory cell selection requires that thebit lines 340 b, 340 c be individually addressed. For example, memorycell 10 b is selected by activating the word line 330 a and the cellselect line 320 b, and by appropriately biasing the bit line 340 b.Similarly, memory cell 10 c is selected by activating word line 330 aand cell select line 320 b, and by appropriately biasing the bit line340 c.

Another improved memory bit structure that results in reduced memory bitarea is illustrated in FIG. 8A. FIG. 8A represents a memory bitstructure 1015 that is similar to the memory bit structure 615 of FIG. 3except that the rectifying devices 660 a, 660 b have been moved so as tobe positioned in between the memory cells 10 a, 10 b and the cell selectlines 320 a, 320 b. The rectifying devices 660 a, 660 b are preferablysilicon p-n diodes or Schottky diodes but are, in this embodiment, notformed within the drains of an access device 350. In the memory bitstructure 1015, one rectifying device can service two memory cells, eachof which is from a different memory bit structure 1015. Thus, thereduction in components results in an overall reduction in memory bitarea.

FIG. 8B illustrates a memory device 1000 that includes a staggeredarrangement of the memory bit structures 1015 a-1015 f. As in the memorydevices 800, 900, the memory cells in memory device 1000 are stacked.This time, however, the cell select lines 320 a-320 d connect first to arectifying device (e.g., 660 a-660 d) and then to the top electrodes ofthe stacked memory cells 10 a-10 h.

FIG. 8C illustrates a cross-sectional view of the physical organizationof two memory bit structures 1015 b, 1015 d in device 1000, in additionto partial depictions of other memory bit structures. The dashed linesin FIG. 8C represent structures that are not in the same viewing planeas those depicted using solid lines. However, by referencing thetop-down view of FIG. 8D, it is apparent that some “solid” structuresare in different planes than other depicted “solid” structures. Asimilar statement may be made regarding the “dashed line” structures. Inother words, the structures depicted in FIG. 8C are located withinmultiple viewing planes; hence FIG. 8C should be viewed in conjunctionwith FIG. 8D.

One of the significant differences between the cross-sectional view ofmemory device 1000 shown in FIG. 8C and the cross-sectional view ofmemory device 800 in FIG. 6B is the absence of the rectifying devices660 a-660 d in the access device drains and the presence of rectifyingdevices 660 a-660 d connected to the cell select lines 320 a, 320 b. Therectifying devices 660 a-660 d are formed by the junction of materiallayers 661, 662. Material layer 661 is formed within the vias connectingthe cell select lines 320 a, 320 b to the memory cells 10 a-10 h.Material layer 662 is formed as a layer directly underneath the cellselect lines 320 a, 320 b. The junction between material layers 661 and662 is a junction between two oppositely doped regions. Material layers661, 662 may be formed of various materials such as doped polysiliconand titanium or platinum, as long as the junction of the two layersforms a rectifying device 660 a-660 d such as a p-n diode or a Schottkydiode.

Similar to that explained above in conjunction with FIG. 6B, memory bitstructure 1015 b (FIG. 8B) includes word line 330 b for activatingaccess device 350 b. When access device 350 b is activated, bit line 340b is coupled to both memory cells 10 a, 10 b. Memory cell 10 a is anupside-down memory cell stacked on top of a memory cell 10 e fromanother memory bit structure. Cell select line 320 a connects withmemory cell 10 a via rectifying device 660 a. Memory cell 10 b is thelower of two stacked memory cells 10 f, 10 b and is coupled to cellselect line 320 b via rectifying device 660 b. Similarly, memory bitstructure 1015 d (FIG. 8B) includes word line 330 c for activatingaccess device 350 d. When access device 350 d is activated, bit line 340b is coupled to both memory cells 10 c, 10 d. Memory cell 10 d is anupside-down memory cell stacked on top of a memory cell 10 h fromanother memory bit structure. Cell select line 320 a connects withmemory cell 10 d via rectifying device 660 d. Memory cell 10 c is thelower of two stacked memory cells 10 g, 10 c and is coupled to cellselect line 320 b via rectifying device 660 c.

FIG. 8D represents a top-down view of the memory bit structures 1015 band 1015 d depicted in FIG. 8C. As in devices 700, 800 and 900, eachactive area 1052 a-1052 c includes two access devices. However, activeareas 1052 a-1052 c are different from the active areas used in devices700, 800 and 900 in that active areas 1052 a-1052 c do not include oneor more rectifying devices. In FIG. 8D, access devices 350 b and 350 dare in the active area 1052 b. Within active area 1052 b, access device350 b is gated by word line 330 b and, when activated, couples bit line340 b to memory cell 10 a (FIG. 8C) located above active area 1052 a andmemory cell 10 b (FIG. 8C) located above active area 1052 b. Similarly,access device 350 d is gated by word line 330 c and, when activated,couples bit line 340 b to memory cell 10 c (FIG. 8C) located aboveactive area 1052 b and memory cell 10 d (FIG. 8C) located above activearea 1052 c. Note that access devices 350 b, 350 d control access tomemory cells that are located in two adjacent but staggered active areas1052 a, 1052 c.

Similar to memory devices 900 and 2300, the bit lines 340 a-340 d indevice 1000 must be appropriately biased in order to select a memorycell. In other words, selection of a memory cell requires selecting thecorresponding word line, cell select line and bit line. Also, therectifying devices 660 b and 660 c may also be merged into onerectifying device connecting a common top electrode similar to memorydevice 900.

A modification to device 1000 is depicted in FIG. 9A. In FIG. 9A, memorydevice 1100 includes a parallel arrangement of memory bit structures1015 a-1015 i. Each memory bit structure 1015 a-1015 i includes a singleaccess device 350 a-350 i and two memory cells (e.g., 10 a-10 d). Thememory cells are stacked with memory cells from adjacent memory bitstructures, as depicted in FIG. 9B. For example, memory cells 10 a, 10 eare stacked; memory cells 10 c, 10 g are also stacked. A rectifyingdevice (e.g., 660 a-660 c) is connected between each memory cell and thecell's corresponding cell select line 320 a-320 d. Significantly, indevice 1100, only one rectifying device is used for up to four memorycells. Each of the four memory cells connected to the same rectifyingdevice is from a different memory bit structure. The rectifying devices660 a-660 c, as described in relation to FIG. 8C, are formed from thejunctions of material layers 661 and 662, wherein the junctionrepresents a boundary between two oppositely doped regions. For example,the top portion of material layer 661 could be n-doped, and the portionof material layer 662 near the junction could p-doped, thus forming ap-n diode. As described above, a Schottky diode may also be formed.

FIG. 9B illustrates a cross-sectional view of the physical organizationof two memory bit structures 1015 a, 1015 d in device 1100, in additionto partial depictions of other memory bit structures. The dashed linesin FIG. 9B represent structures that are not in the same viewing planeas those depicted using solid lines. Also, the structure indicated overactive area 1052 b in FIG. 9B has been shifted for viewing purposes, butis in reality located behind the structure located over active area 1052a (refer to FIG. 9C for further clarity).

In FIG. 9B, cell select lines 320 a, 320 b are connected to the memorycell top electrodes 18 a-18 c via rectifying devices 660 a-660 c. Eachrectifying device 660 a-660 c couples a cell select line 320 a, 320 b tofour memory cells. For example, the structure above active area 1052 adepicts cell select line 320 a coupled to memory cells 10 a, 10 e, 10 c,10 g via rectifying device 660 a. In this way, the number of physicalcomponents or structures per each memory bit structure is reduced, andthe overall structure of device 1100 is simplified. The reduction instructures also allows the memory bit structures 1015 a-1015 i (FIG. 9A)to be fabricated more compactly.

In FIG. 9B, memory bit structures 1015 a and 1015 d are depicted. Inmemory bit structure 1015 a, word line 330 b may be used to activateaccess device 350 a. When access device 350 a is activated, bit line 340b is coupled to both memory cells 10 a, 10 b. Memory cell 10 a is anupside-down memory cell stacked on top of a memory cell 10 e fromanother memory bit structure. Cell select line 320 a connects withmemory cell 10 a via rectifying device 660 a. Memory cell 10 b is thelower of two stacked memory cells 10 f, 10 b and is coupled to cellselect line 320 b via rectifying device 660 b. Similarly, memory bitstructure 1015 d (FIG. 9A) includes word line 330 c for activatingaccess device 350 d. When access device 350 d is activated, bit line 340b is coupled to both memory cells 10 c, 10 d. Memory cell 10 c is anupside-down memory cell stacked on top of a memory cell 10 g fromanother memory bit structure. Cell select line 320 a connects withmemory cell 10 c via rectifying device 660 a. Memory cell 10 d is thelower of two stacked memory cells 10 h, 10 d and is coupled to cellselect line 320 b via rectifying device 660 c.

FIG. 9C represents a top-down view of the memory bit structures 1015 a,1015 d depicted in FIG. 9B. Each active area 1052 a-1052 d includes twoaccess devices. In FIG. 9C, access device 350 a is in the active area1052 b. Access device 350 d is in the active area 1052 d. Within activearea 1052 b, access device 350 a is gated by word line 330 b and, whenactivated, couples bit line 340 b to memory cell 10 a (FIG. 9B) locatedabove active area 1052 a and memory cell 10 b (FIG. 9B) located aboveactive area 1052 b. Similarly, access device 350 d is gated by word line330 c and, when activated, couples bit line 340 b to memory cell 10 c(FIG. 9B) located above active area 1052 a and memory cell 10 d (FIG.9B) located above active area 1052 d. The parallel configuration of theactive areas 1052 a-1052 d results in device 1100 being more dense andarea efficient than devices where the active areas are staggered.

FIGS. 14A-14C represent a similar circuit (memory device 2400 in FIG.14A), organization and arrangement as shown in FIGS. 9A-9C. However, inFIGS. 14A-14C, more than one memory cell shares the same cell selectline and word line. For example, in FIG. 14A, memory bit structures 1015a and 1015 b include memory cells 10 c, 10 d, respectively(among—others). Both memory cells 10 c, 10 d are activated by utilizingcell select line 320 b and word line 330 a. As a result, memory cellselection requires that the bit lines 340 b, 340 c be individuallyaddressed. For example, memory cell 10 c is selected by activating theword line 330 a and the cell select line 320 b, and by appropriatelybiasing the bit line 340 b. Similarly, memory cell 10 d is selected byactivating word line 330 a and cell select line 320 b, and byappropriately biasing the bit line 340 c.

FIG. 10A depicts a memory device 1200 that includes a parallelarrangement of memory bit structures 1015 a-1015 f, organized in a waythat only two memory cells are coupled to a rectifying device. Device1200 makes this possible by spacing the two memory cells controlled bythe same access device at least two access devices apart, as illustratedin FIGS. 10A and 10C. FIG. 10B depicts a cross-sectional view of thephysical structure of two memory bit structures 1015 a, 1015 d fromdevice 1200. FIG. 10C depicts the top-down view of the structures inFIG. 10B. In each of these figures, a memory cell 10 a-10 d shares arectifying device 660 a-660 d with one other memory cell. For example,memory cell 10 a shares rectifying device 660 a with another memory cell10 e upon which memory cell 10 a is stacked. Memory cell 10 c alsoshares access device 350 d with memory cell 10 d. Long metalinterconnects (metal 1 and 2) connect remote memory cells 10 a and 10 cto the access devices 350 a and 350 d, respectively. The metalinterconnects (metal 1 and 2) make it possible to distribute portions ofthe memory bit structure 1015 a, 1015 d to distant active areas (e.g.,1052 a). Effectively, the device 1200 combines the benefits of astaggered active area layout with the compactness of a parallel activearea layout. In device 1200, individual bit lines 340 a-340 d may beindividually addressed accordingly to the cell to be selected.

FIG. 15A represents a memory device 2500 that is similar to memorydevice 1200 of FIG. 10A. FIGS. 15B and 15C represent the correspondingorganization and arrangement of memory device 2500. In memory device2500, more than one memory cell shares the same cell select line andword line. For example, in FIG. 15A, memory bit structures 1015 a and1015 b include memory cells 10 b, 10 c, respectively (among others).Both memory cells 10 b, 10 c are activated by utilizing cell select line320 b and word line 330 a. As a result, memory cell selection requiresthat the bit lines 340 b, 340 c be individually addressed. For example,memory cell 10 b is selected by activating the word line 330 a and thecell select line 320 b, and by appropriately biasing the bit line 340 b.Similarly, memory cell 10 c is selected by activating word line 330 aand cell select line 320 b, and by appropriately biasing the bit line340 c.

The general concepts discussed above can be applied to more complexmemory bit structures. For example, in FIG. 11A, the concepts of memorybit structures 615 (FIG. 3) and 1015 (FIG. 8A) are extended to a oneaccess device/three memory cell memory bit structure 1315. In structure1315, the rectifying devices 660 a-660 c are connected in between thememory cells 10 a-10 c and their respective cell select lines 320 a-320c. In this way, a single access device 350 may control three memorycells 10 a-10 c. In fact, a single access device 350 could controlaccess to as many memory cells as desired using the same basic layoutshown in FIG. 11A. The memory bit structure 1315 may be arranged in amemory device 1300, as represented in FIG. 11B. In FIG. 11B, a cellselect line 320 a-320 i exists for each memory cell in the memory bitstructure 1315 a-13151. Although each memory bit structure 1315 a-13151in device 1300 only depicts three memory cells, as many memory cells asdesired may be added with corresponding cell select lines.

FIG. 11C depicts one possible method of physically arranging the memorybit structures 1315 a, 1315 d. For example, in FIG. 11C, word line 330 ais used to activate access device 350 a, thereby coupling bit line 340 ato the bottom electrodes of memory cells 10 a through 10 x, where ‘x’represents any letter of the alphabet. Each memory cell's top electrodeis also coupled to a cell select line (e.g., 320 a-320 x) via arectifying device (e.g., 660 a-660 x). Memory cell 10 a is connected tocell select line 320 a. Memory cell 10 x is connected to cell selectline 320 x. The memory bit structures 1315 a, 1315 d illustrated in inFIG. 11C are also shown in a top-down view in FIG. 11D. In FIG. 11D, itis apparent that a pair of the memory bit structures (e.g., 1315 a, 1315d) are staggered onto a single active area 1052. In this way, as manymemory cells as desired may be located above a single active area 1052and access device 350 a, 350 d.

Each of the improved phase change memory devices 700-1300 improves thespatial efficiency of phase change memory bit structures by utilizingonly one access device for multiple memory cells. Spatial efficiency isalso improved by stacking memory cells on top of each other and bysharing rectifying devices between memory cells. A parallel arrangementof memory bit structures also results in improved spatial efficiency.

It should be appreciated that the improved phase change memory devices700-1300 may be fabricated as part of an integrated circuit. Thecorresponding integrated circuits may be utilized in a typical processorsystem. For example, FIG. 12 illustrates a simplified processor system1500 which includes a memory device 1400 employing improved phase changememory bit structures such as structures 615, 1015 and 1315 inaccordance with the above described embodiments. A processor system,such as a computer system, generally comprises a central processing unit(CPU) 1510, such as a microprocessor, a digital signal processor, orother programmable digital logic devices, which communicates with aninput/output (I/O) device 1520 over a bus 1590. The memory device 1400communicates with the CPU 1510 over bus 1590 typically through a memorycontroller.

In the case of a computer system, the processor system 1500 may includeperipheral devices such as removable media devices 1550 (e.g., CD-ROMdrive or DVD drive) which communicate with CPU 1510 over the bus 1590.Memory device 1400 is preferably constructed as an integrated circuit,which includes one or more phase change memory devices. If desired, thememory device 1400 may be combined with the processor, for example CPU1510, as a single integrated circuit.

It should also be appreciated that various embodiments have beendescribed as using a phase change material as an exemplary resistancevariable material. The invention may also be used in other types ofresistive memory to improve current flow through whatever resistancevariable material is used.

The above description and drawings should only be consideredillustrative of exemplary embodiments that achieve the features andadvantages described herein. Modification and substitutions to specificprocess conditions and structures can be made. Accordingly, theinvention is not to be considered as being limited by the foregoingdescription and drawings, but is only limited by the scope of theappended claims.

What is claimed is:
 1. A method, comprising: generating, at a memorydevice comprising at least a first memory cell, a cell select signal;transmitting, via a first rectifying device coupled with a cell selectline, the cell select signal to the first memory cell; and activatingthe first memory cell based at least in part on transmitting the cellselect signal to the first memory cell.
 2. The method of claim 1,wherein transmitting the cell select signal to the first memory cellcomprises: passing, by the first rectifying device, the cell selectsignal to the first memory cell.
 3. The method of claim 1, furthercomprising: maintaining a second memory cell of the memory device in adisabled state based at least in part on activating the first memorycell, wherein the second memory cell is coupled with a second rectifyingdevice coupled with a second cell select line.
 4. The method of claim 1,further comprising: reading first data from the first memory cell basedat least in part on activating the first memory cell, wherein readingthe first data from the first memory cell comprises passing a firstcurrent through the first memory cell.
 5. The method of claim 4, furthercomprising: determining a logic state associated with the first dataread from the first memory cell, wherein determining the logic stateassociated with the first data read from the first memory cell comprisesmeasuring, by a sense amplifier, the first current passed through thefirst memory cell.
 6. The method of claim 1, further comprising: writingdata to the first memory cell based at least in part on activating thefirst memory cell, wherein writing the data to the first memory cellcomprises generating a voltage differential between the cell select lineand a digit line coupled with the first memory cell.
 7. The method ofclaim 6, wherein generating the voltage differential between the cellselect line and the digit line coupled with the first memory cellcomprises: altering a voltage of the cell select line, altering avoltage of the digit line coupled with the first memory cell, or acombination thereof.
 8. The method of claim 1, wherein the first memorycell is coupled with the cell select line and an access device via thefirst rectifying device, wherein the access device is coupled with athird memory cell.
 9. The method of claim 8, wherein the access deviceprovides shared access to at least the first memory cell and the thirdmemory cell.
 10. The method of claim 1, wherein at least the firstmemory cell comprises a phase change memory cell.
 11. The method ofclaim 1, wherein at least the first memory cell comprises a resistivememory cell.
 12. The method of claim 1, wherein the first rectifyingdevice comprises a diode.
 13. A method, comprising: transmitting, via acommon electrode positioned between a first memory cell and a secondmemory cell of a memory device, a cell select signal to the first memorycell; coupling, by the common electrode, the first memory cell and thesecond memory cell with a cell select line; receiving, by at least thefirst memory cell, the cell select signal via the common electrode; andactivating the first memory cell based at least in part on receiving thecell select signal via the common electrode.
 14. The method of claim 13,wherein receiving the cell select signal via the common electrodecomprises: passing, by a first rectifying device coupled with the firstmemory cell, the cell select signal to the first memory cell.
 15. Themethod of claim 13, further comprising: maintaining the second memorycell of the memory device in a disabled state based at least in part onactivating the first memory cell, wherein the second memory cell iscoupled with a second rectifying device coupled with a second cellselect line.
 16. The method of claim 13, further comprising: activatingthe cell select line and an access device coupled with the first memorycell, wherein transmitting the cell select signal to the first memorycell is based at least in part on activating the cell select line andthe access device coupled with the first memory cell.
 17. The method ofclaim 13, wherein the first memory cell and the second memory cellcomprise phase change memory cells.
 18. The method of claim 13, whereinthe first memory cell and the second memory cell comprise resistivememory cells.
 19. A method, comprising: generating, at a memory devicecomprising at least a first memory cell, a cell select signal;transmitting, via a first diode coupled with a cell select line, thecell select signal to the first memory cell; activating the first memorycell based at least in part on transmitting the cell select signal tothe first memory cell; and performing an access operation on the firstmemory cell based at least in part on activating the first memory cell.20. The method of claim 19, wherein a first voltage is applied to thecell select line based at least in part on transmitting the cell selectsignal to the first memory cell, wherein performing the access operationon the first memory cell comprises: adjusting the first voltage of thecell select line from the first voltage to a second voltage; and writingdata to the first memory cell based at least in part on adjusting thefirst voltage of the cell select line from the first voltage to thesecond voltage.